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DesignerSun Microsystems (acquired by Oracle Corporation)
Bits64-bit (32 → 64)
Introduced1987 (shipments)
VersionV9 (1993)
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
General purpose31 (G0 = 0; non-global registers use register windows)
Floating point32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
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For other uses, see SPARC (disambiguation).
DesignerSun Microsystems (acquired by Oracle Corporation)
Bits64-bit (32 → 64)
Introduced1987 (shipments)
VersionV9 (1993)
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
General purpose31 (G0 = 0; non-global registers use register windows)
Floating point32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
Sun UltraSPARC II Microprocessor

SPARC (from "scalable processor architecture") is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP and CC-NUMA servers produced by Sun, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006 the complete design of Sun's UltraSPARC T1 microprocessor was released in open-source form at and named the OpenSPARC T1. In 2007 the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form as OpenSPARC T2.[1]

The most recent commercial iterations of the SPARC processor design are the Fujitsu Laboratories Ltd.'s eight core "Venus" 128 GFLOP, 2.0 GHz SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer "K computer", SPARC64 X "Athena" introduced in August 2012,[2] and the 16 core SPARC T5 introduced by Oracle Corporation in March 2013, running at 3.6 GHz.


The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[3][4] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[5]

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2004.[6]

Tagged add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.


There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, IV+ as well as CMT extensions starting with the UltraSPARC T1 implementation:

UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

In August, 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instructions set extensions to 2007 specification.[7]

The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:

SPARC microprocessor specifications[edit]

This table contains specifications for certain SPARC processors: frequency (megahertz), architecture version, release year, number of threads (threads per core multiplied by the number of cores), fabrication process (nanometers), number of transistors (millions), die size (square millimetres), number of I/O pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes).

Name (codename)ModelFrequency (MHz)Arch. versionYearTotal threads[note 1]Process (nm)Transistors (millions)Die size (mm²)IO PinsPower (W)Voltage (V)L1 Dcache (KiB)L1 Icache (KiB)L2 Cache (KiB)L3 Cache (KiB)
SPARC(various), including MB86900[note 2]14.28–40V71987–19921×1=1800–1300~0.1–1.8--160–256----0–128 (unified)nonenone
microSPARC I (Tsunami)TI TMS390S1040–50V819921×1=18000.8225?2882.5524nonenone
SuperSPARC I (Viking)TI TMX390Z50 / Sun STP102033–60V819921×1=18003.1--29314.3516200-2048none
SPARCliteFujitsu MB8683x66–108V8E19921×1=1------144, 176--2.5/3.3V-5.0V, 2.5V-3.3V1, 2, 8, 161, 2, 8, 16nonenone
hyperSPARC (Colorado 1)Ross RT620A40–90V819931×1=15001.5------5?08128-256none
microSPARC II (Swift)Fujitsu MB86904 / Sun STP101260–125V819941×1=15002.323332153.3816nonenone
hyperSPARC (Colorado 2)Ross RT620B90–125V819941×1=14001.5------3.308128-256none
SuperSPARC II (Voyager)Sun STP102175–90V819941×1=18003.1299--16--16201024-2048none
hyperSPARC (Colorado 3)Ross RT620C125–166V819951×1=13501.5------3.308512-1024none
TurboSPARCFujitsu MB86907160–180V819961×1=13503.013241673.51616512none
UltraSPARC (Spitfire)Sun STP1030143–167V919951×1=14703.831552130[note 3]3.31616512-1024none
UltraSPARC (Hornet)Sun STP1030200V919981×1=14205.2265521--3.31616512-1024none
hyperSPARC (Colorado 4)Ross RT620D180–200V819961×1=13501.7------3.31616512none
SPARC64Fujitsu (HAL)101–118V919951×1=1400--Multichip286503.8128128----
SPARC64 IIFujitsu (HAL)141–161V919961×1=1350--Multichip286643.3128128----
SPARC64 IIIFujitsu (HAL) MBCS70301250–330V919981×1=124017.6240----2.564648192--
UltraSPARC IIs (Blackbird)Sun STP1031250–400V919971×1=13505.414952125[note 4]2.516161024 or 4096none
UltraSPARC IIs (Sapphire-Black)Sun STP1032 / STP1034360–480V919991×1=12505.412652121[note 5]1.916161024–8192none
UltraSPARC IIi (Sabre)Sun SME1040270–360V919971×1=13505.4156587211.91616256–2048none
UltraSPARC IIi (Sapphire-Red)Sun SME1430333–480V919981×1=12505.4--58721[note 6]1.916162048none
UltraSPARC IIe (Hummingbird)Sun SME1701400–500V919991×1=1180 Al----37013[note 7]1.5-1.71616256none
UltraSPARC IIi (IIe+) (Phantom)Sun SME1532550–650V920001×1=1180 Cu----37017.61.71616512none
SPARC64 GPFujitsu SFCB81147400–563V920001×1=118030.2217----1.81281288192--
SPARC64 GP--600–810V9--1×1=115030.2------1.51281288192--
SPARC64 IVFujitsu MBCS80523450–810V920001×1=1130----------1281282048--
UltraSPARC III (Cheetah)Sun SME1050600V9 / JPS120011×1=1180 Al293301368531.664328192none
UltraSPARC III (Cheetah)Sun SME1052750–900V9 / JPS120011×1=1130 Al29--1368--1.664328192none
UltraSPARC III Cu (Cheetah+)Sun SME10561002–1200V9 / JPS120011×1=1130 Cu29232136880[note 8]1.664328192none
UltraSPARC IIIi (Jalapeño)Sun SME16031064–1593V9 / JPS120031×1=113087.5206959521.364321024none
SPARC64 V (Zeus)Fujitsu1100–1350V9 / JPS120031×1=1130190289269401.21281282048--
SPARC64 V+ (Olympus-B)Fujitsu1650–2160V9 / JPS120041×1=1904002972796511281284096--
UltraSPARC IV (Jaguar)Sun SME11671050–1350V9 / JPS120041×2=21306635613681081.35643216384none
UltraSPARC IV+ (Panther)Sun SME1167A1500–2100V9 / JPS120051×2=2902953361368901.16464204832768
UltraSPARC T1 (Niagara)Sun SME19051000–1400V9 / UA 200520054×8=32903003401933721.38163072none
SPARC64 VI (Olympus-C)Fujitsu2150–2400V9 / JPS120072×2=490540422--120–1501.1128x2128x24096–6144none
UltraSPARC T2 (Niagara 2)Sun SME1908A1000–1600V9 / UA 200720078×8=64655033421831951.1–1.58164096none
UltraSPARC T2 Plus (Victoria Falls)Sun SME1910A1200–1600V9 / UA 200720088×8=64655033421831--8164096none
SPARC64 VII (Jupiter)[8]Fujitsu2400–2880V9 / JPS120082×4=865600445--150--64x464x46144none
UltraSPARC "RK" (Rock)[9]Sun SME18322300V9 / --canceled[10]2×16=3265?3962326??32322048?
SPARC64 VIIIfx (Venus)[11][12]Fujitsu2000V9 / JPS120091x8=845760513127158?32x832x86144none
SPARC T3 (Rainbow Falls)Oracle/Sun1650V9 / UA _?_20108×16=12840[13]????371?139?8166144none
SPARC64 VII+ (Jupiter-E or M3)[14][15]Fujitsu2667-3000V9 / JPS120102x4=865---160-64x464x412288none
MCST-4RMCST (Russia)750-1000V920101x4=490150115-15132162048none
SPARC T4 (Yosemite Falls)[16]Oracle2850-3000V9 / OSA2011?20118×8=6440855403?240?16x816x8128x84096
SPARC64 IXfx[17][18]Fujitsu1850V9 / JPS1?20121x16=164018704841442110?32x1632x1612288none
SPARC64 X (Athena)Fujitsu2800V9 / JPS20122x16=32282950587.51500270?64x1664x1624576none
SPARC T5Oracle3600V9 / OSA2011?20138×16=128281500478???16x1616x16128x168192
SPARC M5Oracle3600V9 / OSA2011?20138×6=48283900????16x616x6128x649152
SPARC M6Oracle3600V9 / OSA2011?20138×12=9628?????16x1216x12128x1249152
SPARC64 X+ (Athena+)Fujitsu3200V9 / JPS20142x16=322829906001500392?64x1664x1624Mnone
SPARC64 XIfxFujitsu2200V9 / JPS?2015?1x(32+2)=34203750?1001??64x3464x3412Mx2none
SPARC M7[19][20] [21]Oracle>3600?2015?8x32=25620>10000????16x3216x32256x2465536
Name (codename)ModelFrequency (MHz)Arch. versionYearTotal threads[note 1]Process (nm)Transistors (millions)Die size (mm²)IO PinsPower (W)Voltage (V)L1 Dcache (k)L1 Icache (k)L2 Cache (k)L3 Cache (k)


  1. ^ a b Threads per core × number of cores
  2. ^ Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments and Cypress. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory.
  3. ^ @167 MHz
  4. ^ @250 MHz
  5. ^ @400 MHz
  6. ^ @440 MHz
  7. ^ max@500 MHz
  8. ^ @900 MHz

Operating system support[edit]

SPARC machines have generally used Sun's SunOS, Solaris or OpenSolaris, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[22] but it was later cancelled.

Open source implementations[edit]

Three fully open source implementations of the SPARC architecture exist:

A fully open source simulator for the SPARC architecture also exists:


Fujitsu's K computer ranked #1 in TOP500 - June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500 at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any other supercomputer system.[23] It also ranked #6 in Green500 - June 2011 list, with a score of 824.56 MFLOPS/W.[24] In the November 2012 release of TOP500, the K computer ranked #3, using by far the most power of the top three.[25] It ranked #85 on the corresponding Green500 release.[26]

Tianhe-1A (TOP500 #8 as of November 2012[25]) has a number of nodes with FeiTeng-1000 SPARC-based processors developed in China (based on OpenSPARC). However, those processors did not contribute to the LINPACK score.[27][28]

On Dec. 2, 2010, Oracle unveiled the SPARC SuperCluster with T3-2, T3-4 and M5000 servers.[29] The configuration with T3-4 servers was claimed to surpass the HP Integrity Superdome and the IBM Power 780 server, reaching speeds of 30,249,688 tpmC.[30]

See also[edit]


  1. ^ OpenSPARC T2, OpenSPARC (Oracle Corporation), retrieved 2011-11-06 
  2. ^ "SPARC64™X: Fujitsu’s New Generation 16 Core Processor for the next generation UNIX servers". Fujitsu. 2012-08-29. Retrieved 2013-01-08. 
  3. ^ SPARC Options, Using the GNU Compiler Collection (GCC) (GNU), retrieved 2013-01-08 
  4. ^ SPARC Optimizations With GCC, OSNews, 2004-02-23, retrieved 2013-01-08 
  5. ^ Weaver, D. L.; Germond, T., eds. (1994), The SPARC Architecture Manual, Version 9, SPARC International, Inc. (Prentice Hall), ISBN 0-13-825001-4, retrieved 2011-12-06 
  6. ^ "SPARC Behavior and Implementation". Numerical Computation Guide — Sun Studio 10. Sun Microsystems, Inc. 2004. Retrieved 2011-09-24. "There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC FPU)." 
  7. ^ Oracle SPARC Architecture 2011, Oracle Corporation, 2012-08-03, retrieved 2013-01-31 
  8. ^ FX1 Key Features & Specifications, Fujitsu, 2008-02-19, retrieved 2011-12-06 
  9. ^ Tremblay, Marc; Chaudhry, Shailender (2008-02-19), A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor, OpenSPARC (Sun Microsystems), retrieved 2011-12-06 
  10. ^ Vance, Ashlee (2009-06-15), Sun Is Said to Cancel Big Chip Project, The New York Times, retrieved 2010-05-23 
  11. ^ Fujitsu shows off SPARC64 VII, heise online, 2008-08-28, retrieved 2011-12-06 
  12. ^ Barak, Sylvie (2009-05-14), Fujitsu unveils world’s fastest CPU, The Inquirer, retrieved 2011-12-06 
  13. ^ Sparc T3 processor, Oracle Corporation, retrieved 2011-12-06 
  14. ^ Morgan, Timothy Prickett (2010-12-03), Ellison: Sparc T4 due next year, The Register, retrieved 2011-12-06 
  15. ^ SPARC Enterprise M-series Servers Architecture, Fujitsu, April 2011 
  16. ^ Morgan, Timothy Prickett (2011-08-22), Oracle's Sparc T4 chip, The Register, retrieved 2011-12-06 
  17. ^ Morgan, Timothy Prickett (2011-11-21), Fujitsu parades 16-core Sparc64 super stunner, The Register, retrieved 2011-12-08 
  18. ^ Fujitsu Launches PRIMEHPC FX10 Supercomputer, Fujitsu, 2011-11-07, retrieved 2012-02-03 
  19. ^
  20. ^
  21. ^
  22. ^ McLaughlin, John (1993-07-07), Intergraph to Port Windows NT to SPARC, The Florida SunFlash 55 (11), retrieved 2011-12-06 
  23. ^ TOP500 List (1-100), TOP500, June 2011, retrieved 2011-12-06 
  24. ^ The Green500 List, Green500, June 2011 
  25. ^ a b Top500 List - November 2012 | TOP500 Supercomputer Sites, TOP500, November 2012, retrieved 2013-01-08 
  26. ^ The Green500 List - November 2012 | The Green500, Green500, November 2012, retrieved 2013-01-08 
  27. ^ Keane, Andy, Tesla Supercomputing (mp4), Nvidia, retrieved 2011-12-06 
  28. ^ U.S. says China building 'entirely indigenous' supercomputer, by Patrick Thibodeau Computerworld, November 4, 2010 [1]
  29. ^ Oracle Announces New SPARC Supercluster, Oracle, 2010-12-02, retrieved 2011-12-06 
  30. ^ Oracle Beats IBM with Nearly Three Times Better Throughput, Oracle, 2010-12-02, retrieved 2011-12-06 

External links[edit]