This article is about NAND Logic in the sense of building other logic gates using just NAND gates. For NAND Gates, see NAND gate. For NAND in the purely logical sense, see Logical NAND. For logic gates generally, see Logic gate.
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Because the NAND function has functional completeness all logic systems can be converted into NAND gates. This is also true of NOR gates. Functional completeness allows to modify initial logic system design that may use various types of gates to only use NAND gates. Low number of transistors required to implement a NAND gate allows for better space efficiency, lower propagation delays and reduced system cost.
A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.
If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.
An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low.
Desired XOR Gate
NAND Construction
Q = A XOR B
= NOT[ NOT{A AND NOT(A AND B)} AND NOT{B AND NOT(A AND B)} ]