NAND logic

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Because the NAND function has functional completeness all logic systems can be converted into NAND gates. This is also true of NOR gates.
Functional completeness allows to modify initial logic system design that may use various types of gates to only use NAND gates. Low number of transistors required to implement a NAND gate allows for better space efficiency, lower propagation delays and reduced system cost.

NAND[edit]

A NAND gate is an inverted AND gate. It has the following truth table:

NAND ANSI Labelled.svg

Q = NOT( A AND B )

Truth Table
Input AInput BOutput Q
001
011
101
110

NOT[edit]

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

Desired NOT GateNAND Construction
NOT ANSI Labelled.svgNOT from NAND.svg
Q = NOT( A )= NOT( A AND A )
Truth Table
Input AOutput Q
01
10

AND[edit]

An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND.

Desired AND GateNAND Construction
AND ANSI Labelled.svgAND from NAND.svg
Q = A AND B= NOT( NOT( A AND B ))
Truth Table
Input AInput BOutput Q
000
010
100
111

OR[edit]

If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

Desired OR GateNAND Construction
OR ANSI Labelled.svgOR from NAND.svg
Q = A OR B= NOT[ NOT( A AND A ) AND NOT( B AND B )]
Truth Table
Input AInput BOutput Q
000
011
101
111

NOR[edit]

A NOR gate is simply an inverted OR gate. Output is high when neither input A nor input B is high:

Desired NOR GateNAND Construction
NOR ANSI Labelled.svgNOR from NAND.svg
Q = NOT( A OR B )= NOT{ NOT[ NOT( A AND A ) AND
NOT( B AND B )]}
Truth Table
Input AInput BOutput Q
001
010
100
110

XOR[edit]

An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low.

Desired XOR GateNAND Construction
XOR ANSI Labelled.svgXOR from NAND.svg
Q = A XOR B= NOT[ NOT{A AND NOT(A AND B)} AND
NOT{B AND NOT(A AND B)} ]
Truth Table
Input AInput BOutput Q
000
011
101
110

XNOR[edit]

An XNOR gate is simply an XOR gate with an inverted output:

Desired XNOR GateNAND Construction
XNOR ANSI Labelled.svgXNOR from NAND.svg
Q = NOT( A XOR B)= NOT[ NOT[ NOT{A AND NOT(A AND B)} AND
NOT{B AND NOT(A AND B)} ] ]
Truth Table
Input AInput BOutput Q
001
010
100
111

External links[edit]

See also[edit]

References[edit]

Lancaster, Don (1974). TTL Cookbook (1st ed.). Indianapolis, IN: Howard W Sams. pp. 126–135. ISBN 0-672-21035-5.