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A memory rank is a set of DRAM chips connected to the same chip select, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).
The term “rank” was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit wide data bus (with an optional extra 8-bit chip ECC on some DIMMs). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8-bit) DRAMs would consist of 8 physical chips (plus one for ECC), but a rank of x4 (4-bit) DRAMs would consist of 16 physical chips (plus two for ECC). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).
There is little difference between a dual rank UDIMM and two single rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs. The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increases memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. DRAM load on the CA (Command/Address) bus can be reduced by using registered memory.
From a performance point of view there are several aspects: