Low-dropout regulator

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Schematic of a low-dropout regulator

A low-dropout or LDO regulator is a DC linear voltage regulator which can operate with a very small input–output differential voltage.[1] The advantages of a low dropout voltage include a lower minimum operating voltage, higher efficiency operation and lower heat dissipation.[2]

The main components are a power FET and a differential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes to maintain a constant output voltage.

For the circuit given in the figure the output voltage is given as

 V_{out}= \left( 1 + \frac{R_2}{R_1} \right) V_{ref}



The adjustable low-dropout regulator debuted on April 12, 1977 in an Electronic Design article entitled "Break Loose from Fixed IC Regulators". The article was written by Robert Dobkin, an IC designer then working for National Semiconductor. Because of this, National Semiconductor claims the title of "LDO inventor".[3] Dobkin later left National in 1981 and founded Linear Technology where he is currently chief technology officer.[4]


Low-dropout (LDO) regulators work in the same way as all linear voltage regulators. The main difference between LDO and non-LDO regulators is their schematic topology. Instead of an emitter follower topology, low-dropout regulators utilize open collector or open drain topology. This enables transistor saturation, which allows the voltage drop from the unregulated voltage to the regulated voltage to be as low as the saturation voltage across the transistor.

If a bipolar transistor is used, as opposed to a field-effect transistor or JFET, significant additional power may be lost to control it, whereas non-LDO regulators take that power from voltage drop itself. For high voltages under very low In-Out difference there will be significant power loss in the control circuit.[5]

Because the power control element functions as an inverter, another inverting amplifier is required to control it, which increases schematic complexity compared to a simple voltage stabilizer.[citation needed]

Power FETs may be preferable to reduce power consumption, but this poses problems when the regulator is used for low input voltage, as FETs usually require 5 to 10V to close completely. Power FETs may also increase the cost.

Quiescent current

Among other important characteristics is the quiescent current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input–output drop limit the efficiency of LDO regulators and should thus be minimized.


LDO is characterized by its drop-out voltage, quiescent current, load regulation, line regulation, maximum current (which is decided by the size of the pass transistor), speed (how fast it can respond as the load varies), voltage variations in the output because of sudden transients in the load current, output capacitor and its equivalent series resistance.[6] Speed is indicated by the rise time of the current at the output as it varies from 0mA load current (no load) to the maximum load current. This is basically decided by the bandwidth of the error amplifier. One should also make sure that there is no positive feedback. So there is a need to do frequency compensation either internally or externally by having only one pole (dominant pole) within its UGB.

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