Intel Core (microarchitecture)

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Intel Core
Intel Core 2 Quad.png
L1 cache64 kB per core
L2 cache1 MB to 8 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
PredecessorEnhanced Pentium M
SuccessorPenryn (tick)
Nehalem (tock)
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This article is about the Intel microarchitecture. For Intel processors branded as Intel Core, see Intel Core.
Intel Core
Intel Core 2 Quad.png
L1 cache64 kB per core
L2 cache1 MB to 8 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
PredecessorEnhanced Pentium M
SuccessorPenryn (tick)
Nehalem (tock)

The Intel Core microarchitecture (previously known as the Next-Generation Micro-Architecture) is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based on the Yonah processor design and can be considered an iteration of the P6 microarchitecture, introduced in 1995 with Pentium Pro. The high power consumption and heat intensity, the resulting inability to effectively increase clock speed, and other shortcomings such as the inefficient pipeline were the primary reasons for which Intel abandoned the NetBurst microarchitecture and switched to completely different architectural design, delivering high efficiency through a small pipeline rather than high clock speeds. The Core microarchitecture never reached the clock speeds of the Netburst microarchitecture, even after moving to the 45 nm lithography.

The first processors that used this architecture were code-named Merom, Conroe, and Woodcrest; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. Mainstream Core-based processors are branded Pentium Dual-Core or Pentium and low end branded Celeron; server and workstation Core-based processors are branded Xeon, while desktop and mobile Core-based processors are branded as Core 2. Despite their names, processors sold as Core Solo/Core Duo and Core i3/i5/i7 do not actually use the Core microarchitecture and are based on the Enhanced Pentium M and newer Nehalem/Sandy Bridge/Haswell microarchitectures, respectively.


The Core microarchitecture returned to lower clock rates and improved the usage of both available clock cycles and power when compared with the preceding NetBurst microarchitecture of the Pentium 4/D-branded CPUs.[1] The Core microarchitecture provides more efficient decoding stages, execution units, caches, and buses, reducing the power consumption of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in the CPU power dissipation tables.

Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as Intel VT-x), as well as Intel 64 and SSSE3. However, Core-based processors do not have the Hyper-Threading Technology found in Pentium 4 processors. This is because the Core microarchitecture is a descendant of the P6 microarchitecture used by Pentium Pro, Pentium II, Pentium III, and Pentium M.

The L1 cache size was enlarged in the Core microarchitecture, from 32KB on Pentium II/III (16 KB L1 Data + 16 KB L1 Instruction) to 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) on Pentium M and Core/Core 2. It also lacks an L3 Cache found in the Gallatin core of the Pentium 4 Extreme Edition, although an L3 Cache is present in high-end versions of Core-based Xeons. Both an L3 cache and Hyper-threading were reintroduced in the Nehalem microarchitecture.


Main article: Intel Tick-Tock


While the Core microarchitecture is a major architectural revision it is based in part on the Pentium M processor family designed by Intel Israel.[2] The Penryn pipeline is 12–14 stages long[3] — less than half of Prescott's, a signature feature of wide order execution cores. Penryn's successor, Nehalem has 14 pipeline stages.[3] Core's execution unit is 4 issues wide, compared to the 3-issue cores of P6, Pentium M, and 2-issue cores of NetBurst microarchitectures. The new architecture is a dual core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt and improved scalability.

One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. Unfortunately, this technology does not work in 64-bit mode.

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, as well as Intel's own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and consume as little power as possible.

Intel Core microarchitecture.

For most Woodcrest CPUs, the front side bus (FSB) runs at 1333 MT/s; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants.[4][5] The Merom mobile variant was initially targeted to run at a FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22, 2007.

The power consumption of these new processors is extremely low—average use energy consumption is to be in the 1–2 watt range in ultra low voltage variants, with thermal design powers (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 watts for the low-voltage Woodcrest. In comparison, an AMD Opteron 875HE processor consumes 55 watts, while the energy efficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions.[citation needed]

Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at IDF in the spring of 2006, Intel advertised both. Some of the promised numbers were:

Processor cores[edit]

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

fabcoresMobileDesktop, UP ServerCL ServerDP ServerMP Server
Single-Core 65 nm65 nm1Merom-L
Single-Core 45 nm45 nm1Penryn-L
Dual-Core 65 nm65 nm2Merom-2M
Dual-Core 45 nm45 nm2Penryn-3M
Quad-Core 65 nm65 nm4Kentsfield
Quad-Core 45 nm45 nm4Penryn-QC
Dunnington QC
Six-Core 45 nm45 nm6Dunnington

Conroe/Merom (65 nm)[edit]

The original Core 2 processors are based around the same dies that can be identified as CPUID Family 6 Model 15. Depending on their configuration and packaging, their code names are Conroe (LGA 775, 4 MB L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom (Socket M, 4 MB L2 cache) and Kentsfield (Multi-chip module, LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features can be found in Pentium Dual Core and Celeron processors, while Conroe, Allendale and Kentsfield also are sold as Xeon processors.

Additional code names for processors based on this model are Woodcrest (LGA 771, 4 MB L2 cache), Clovertown (MCM, LGA 771, 2×4MB L2 cache) and Tigerton (MCM, Socket 604, 2×4MB L2 cache), all of which are marketed only under the Xeon brand.

ProcessorBrand nameModel (list)CoresL2 CacheSocketTDP
Merom-2MMobile Core 2 DuoU7xxx22 MiBBGA47910 W
MeromL7xxx4 MiB17 W
2–4 MiBSocket M
Socket P
35 W
MeromMobile Core 2 ExtremeX7xxx24 MiBSocket P44 W
MeromCeleron M5x01512 KiBSocket M
Socket P
30 W
Merom-2M5x5Socket P31 W
Merom-2MCeleron Dual-CoreT1xxx2512–1024 KiBSocket P35 W
Merom-2MPentium Dual-CoreT2xxx
21 MiBSocket P35 W
AllendaleXeon3xxx22 MBLGA 77565 W
Conroe3xxx2–4 MB
Conroe and
Core 2 DuoE4xxx22 MBLGA 77565 W
E6xx02–4 MB
Conroe-CLE6xx52–4 MBLGA 771
Conroe-XECore 2 ExtremeX6xxx24 MBLGA 77575 W
AllendalePentium Dual-CoreE2xxx21 MBLGA 77565 W
AllendaleCeleronE1xxx2512 kBLGA 77565 W
KentsfieldXeon32xx42×4 MiBLGA 77595–105 W
KentsfieldCore 2 QuadQ6xxx42×4 MiBLGA 77595–105 W
Kentsfield XECore 2 ExtremeQX6xxx42×4 MiBLGA 775130 W
WoodcrestXeon51xx24 MBLGA 77165–80 W
ClovertownL53xx42×4 MBLGA 77140–50 W
E53xx80 W
X53xx120–150 W
Tigerton-DCE72xx22×4 MBSocket 60480 W
TigertonL73xx450 W
E73xx2×2–2×4 MB80 W
X73xx2×4 MB130 W


The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.

ProcessorBrand nameModel (list)CoresL2 CacheSocketTDP
Merom-LMobile Core 2 SoloU2xxx12 MiBBGA4795.5 W
Merom-LCeleron M5x01512 KiBSocket M
Socket P
27 W
Merom-L5x3512–1024 KiBBGA4795.5–10 W
Conroe-LCeleron M4x01512 KiBLGA 77535 W
Conroe-CL4x5LGA 77165 W

Penryn/Wolfdale (45 nm)[edit]

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

ProcessorBrand nameModel (list)CoresL2 CacheSocketTDP
Penryn-LCore 2 SoloSU3xxx13 MiBBGA9565.5 W
Penryn-3MCore 2 DuoSU7xxx23 MBBGA95610 W
PenrynSL9xxx6 MiB17 W
SP9xxx25/28 W
Penryn-3MP7xxx3 MiBSocket P
25 W
PenrynP9xxx6 MiB
Penryn-3MT6xxx2 MiB35 W
T8xxx3 MiB
PenrynT9xxx6 MiB
E8x356 MiBSocket P35-55 W
Penryn-QCCore 2 QuadQ9xxx42x3-2x6 MiBSocket P45 W
Penryn XECore 2 ExtremeX9xxx26 MiBSocket P44 W
Penryn-QCQX9xxx42x6 MiB45 W
Penryn-3MCeleronT3xxx21 MiBSocket P35 W
SU2xxxµFC-BGA 95610 W
Penryn-L9x011 MiBSocket P35 W
7x3µFC-BGA 95610 W
Penryn-3MPentiumT4xxx21 MiBSocket P35 W
SU4xxx2 MiBµFC-BGA 95610 W
Penryn-LSU2xxx15.5 W
CeleronE3xxx21 MBLGA 77565 W
E5xxx2 MB
Core 2 DuoE7xxx3 MB
WolfdaleE8xxx6 MB
Xeon31x045-65 W
Wolfdale-CL30x41LGA 77130 W
31x3265 W
YorkfieldXeonX33x042×3–2×6 MBLGA 77565–95 W
Yorkfield-CLX33x3LGA 77180 W
Yorkfield-6MCore 2 QuadQ8xxx2×2 MBLGA 77565–95 W
Q9x0x2×3 MB
YorkfieldQ9x5x2×6 MB
Yorkfield XECore 2 ExtremeQX9xxx2×6 MB130–136 W
QX9xx5LGA 771150 W
Wolfdale-DPXeonE52xx26 MBLGA 77165 W
L52xx20-55 W
X52xx80 W
HarpertownE54xx42×6 MBLGA 77180 W
L54xx40-50 W
X54xx120-150 W


The Xeon "Dunnington" processor (CPUID Family 6, model 29) is closely related to Wolfdale but comes with six cores and an on-chip L3 cache and is designed for servers with Socket 604, so it is marketed only as Xeon, not as Core 2.

ProcessorBrand nameModel (list)CoresL3 CacheSocketTDP
DunningtonXeonE74xx4-68-16 MBSocket 60490 W
L74xx4-612 MB50-65 W
X7460616 MB130 W


The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.

Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.

Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.

Steppings using 65 nm process[edit]

Mobile (Merom)Desktop (Conroe)Desktop (Kentsfield)Server (Woodcrest, Clovertown, Tigerton)
SteppingReleasedAreaCPUIDL2 cacheMax. clockCeleronPentiumCore 2CeleronPentiumCore 2XeonCore 2XeonXeon
B2Jul 2006143 mm²06F64 MiB2.93 GHzM5xxT5000 T7000 L7000E6000 X600030005100
B3Nov 2006143 mm²06F74 MiB3.00 GHzQ6000 QX600032005300
L2Jan 2007111 mm²06F22 MiB2.13 GHzT5000 U7000E2000E4000 E60003000
E1May 2007143 mm²06FA4 MiB2.80 GHzM5xxT7000 L7000 X7000
G0Apr 2007143 mm²06FB4 MiB3.00 GHzM5xxT7000 L7000 X7000E2000E4000 E60003000Q6000 QX600032005100 5300 7200 7300
G2Mar 2009143 mm²06FB4 MiB2.16 GHzM5xxT5000 T7000 L7000
M0Jul 2007111 mm²06FD2 MiB2.40 GHz5xx T1000T2000 T3000T5000 T7000 U7000E1000E2000E4000
A1Jun 200781 mm²106611 MiB2.20 GHzM5xxU2000220 4x0

Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.

The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.

The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.

Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2.[6]

Steppings using 45 nm process[edit]

Mobile (Penryn)Desktop (Wolfdale)Desktop (Yorkfield)Server (Wolfdale-DP, Harpertown, Dunnington)
SteppingReleasedAreaCPUIDL2 cacheMax. clockCeleronPentiumCore 2CeleronPentiumCore 2XeonCore 2XeonXeon
C0Nov 2007107 mm²106766 MiB3.00 GHzE8000 P7000 T8000 T9000 P9000 SP9000 SL9000 X9000E80003100QX90005200 5400
M0Mar 200882 mm²106763 MiB2.40 GHz7xxSU3000 P7000 P8000 T8000 SU9000E5000 E2000E7000
C1Mar 2008107 mm²106776 MiB3.20 GHzQ9000 QX90003300
M1Mar 200882 mm²106773 MiB2.50 GHzQ8000 Q90003300
E0Aug 2008107 mm²1067A6 MiB3.33 GHzT9000 P9000 SP9000 SL9000 Q9000 QX9000E80003100Q9000 Q9000S QX900033005200 5400
R0Aug 200882 mm²1067A3 MiB2.93 GHz7xx 900 SU2000 T3000T4000 SU2000 SU4000SU3000 T6000 SU7000 P8000 SU9000E3000E5000 E6000E7000Q8000 Q8000S Q9000 Q9000S3300
A1Sep 2008503 mm²106D13 MiB2.67 GHz7400

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.

Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[7] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).

System requirements[edit]

Motherboard compatibility[edit]

Conroe, Conroe XE and Allendale all use Socket LGA 775; however, not every motherboard is compatible with these processors.

Supporting chipsets are:

See also: List of Intel chipsets

The currently released Yorkfield XE model QX9770 (45 nm with 1600FSB) currently has limited chipset compatibility - with only X38, P35 (With Overclocking) and some high-performance X48 and P45 motherboards being compatible. BIOS updates are gradually being released to provide support for the new Penryn technology, and the new QX9775 is only compatible with D5400XS. The Wolfdale-3M model E7200 also has limited compatibility (at least the Xpress 200 chipset is incompatible)[citation needed].

Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above-mentioned chipsets do not support Conroe. This is because all Conroe-based processors require a new power delivery feature set specified in Voltage Regulator-Down (VRD) 11.0. This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it is replacing. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated BIOS to recognize Conroe's FID (Frequency ID) and VID (Voltage ID).

Synchronous memory modules[edit]

Unlike the previous Pentium 4 and Pentium D design, the Core 2 technology sees a greater benefit from memory running synchronously with the Front Side Bus (FSB). This means that for the Conroe CPUs with FSB of 1066 MT/s, the ideal memory performance for DDR2 is PC2-8500. In a few configurations, using PC2-5300 instead of PC2-4200 can actually decrease performance. Only when going to PC2-6400 is there a significant performance increase. While DDR2 memory models with tighter timing specifications do improve performance, the difference in real world games and applications is often negligible.[8]

Optimally, the memory bandwidth afforded should match the bandwidth of the FSB, that is to say that a CPU with a 533 MT/s rated bus speed should be paired with RAM matching the same rated speed, for example DDR2 533, or PC2-4200. A common myth[citation needed] is that installing interleaved RAM will offer double the bandwidth. However, at most the increase in bandwidth by installing interleaved RAM is roughly 5–10%. The AGTL+ PSB[dead link] used by all NetBurst processors as well as current and medium-term (pre-QuickPath) Core 2 processors provide a 64-bit data path. Current chipsets provide for a couple of either DDR2 or DDR3 channels.

Matched processor and RAM ratings
Processor modelFront side busMatched memory and maximum bandwidth
single channel / dual channel
mobile: T5200, T5300, U2n00, U7n00533 MT/sPC-3200 (DDR-400)
3.2 GB/s
PC2-4200 (DDR2-533)
4.264 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/s
PC3-8500 (DDR3-1066)
8.530 GB/s
desktop: E6n00, E6n20, X6n00, E7n00, Q6n00 and QX6n00
mobile: T9400, T9550, T9600, P7350, P7450, P8400, P8600, P8700, P9500, P9600, SP9300, SP9400, X9100
1066 MT/s
mobile: T5n00, T5n50, T7n00 (Socket M), L7200, L7400667 MT/sPC-3200 (DDR-400)
3.2 GB/s
PC2-5300 (DDR2-667)
5.336 GB/s
PC3-10600 (DDR3-1333)
10.670 GB/s
desktop: E6n40, E6n50, E8nn0, Q9nn0, QX6n50, QX96501333 MT/s
mobile: T5n70, T6400, T7n00 (Socket P), L7300, L7500, X7n00, T8n00, T9300, T9500, X9000
desktop: E4n00, Pentium E2nn0, Pentium E5nn0, Celeron 4n0, E3n00
800 MT/sPC-3200 (DDR-400)
3.2 GB/s
PC-3200 (DDR-400)
3.2 GB/s
PC2-6400 (DDR2-800)
6.400 GB/s
PC2-8500 (DDR2-1066)
8.532 GB/s
PC3-6400 (DDR3-800)
6.400 GB/s
PC3-12800 (DDR3-1600)
12.800 GB/s
desktop: QX9770, QX97751600 MT/s

On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit significantly[9] from using a PC2-8500 memory, which runs exactly the same speed as the CPU's FSB; this is not an officially supported configuration, but a number of motherboards offer it.

The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both the Core 2 and DDR memory. When using DDR memory, performance may be reduced because of the lower available memory bandwidth.

Chip errata[edit]

The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors does not operate to previous specifications implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the translation lookaside buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data."[10]

Among the issues stated:

Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious.[11] 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings.

Among those who have stated the errata to be particularly serious are OpenBSD's Theo de Raadt[12] and DragonFly BSD's Matthew Dillon.[13] Taking a contrasting view was Linus Torvalds, calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better."[14]

Microsoft has issued update KB936357 to address the errata by microcode update,[15] with no performance penalty. BIOS updates are also available to fix the issue.

Key Terms[edit]

MT/s. Millions of transfers/second, each transfer on the Intel Core architecture is 32-bits.

See also[edit]


  1. ^ "Penryn Arrives: Core 2 Extreme QX9650 Review". ExtremeTech. Retrieved 2006-10-30. [dead link]
  2. ^ King, Ian (2007-04-09). "How Israel saved Intel". The Seattle Times. Retrieved 2012-04-15. 
  3. ^ a b Swinburne, Richard (3 November 2008). "Intel Core i7 - Nehalem Architecture Dive: 5 - Architecture Enhancements". Retrieved 21 August 2011. 
  4. ^ "Intel Xeon Processor 5110". Intel. Retrieved 2012-04-15. 
  5. ^ "Intel Xeon Processor 5120". Intel. Retrieved 2012-04-15. 
  6. ^ "Product Change Notice" (PDF). Retrieved 2012-06-17. 
  7. ^ "ARK entry for Intel Xeon Processor X7460". Intel. Retrieved 14 July 2009. 
  8. ^ piotke (2006-08-01). "Intel Core 2: Is high speed memory worth its price?". Madshrimps. Retrieved 2006-08-01. 
  9. ^ Jacob (2007-05-19). "Benchmarks of four Prime95 processes on a quad-core". Mersenne Forum. Retrieved 2007-05-22. 
  10. ^ "Dual-Core Intel Xeon Processor 7200 Series and Quad-Core Intel Xeon Processor 7300 Series" (PDF). p. 46. Retrieved 2010-01-23. 
  11. ^ "Intel Core 2 Duo Processor for Intel Centrino Duo Processor Technology Specification Update" (PDF). pp. 18–21. 
  12. ^
  13. ^ "Matthew Dillon on Intel Core Bugs". OpenBSD journal. 2007-06-30. Retrieved 2012-04-15. 
  14. ^ Torvalds, Linus (2007-06-27). "Core 2 Errata -- problematic or overblown?". Real World Technologies. Retrieved 2012-04-15. 
  15. ^ "A microcode reliability update is available that improves the reliability of systems that use Intel processors". Microsoft. 2011-10-08. Retrieved 2012-04-15. 

External links[edit]