IOMMU

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Comparison of the I/O memory management unit (IOMMU) to the memory management unit (MMU).

In computing, an input/output memory management unit (IOMMU) is a memory management unit (MMU) that connects a direct memory access-capable (DMA-capable) I/O bus to the main memory. Like a traditional MMU, which translates CPU-visible virtual addresses to physical addresses, the IOMMU maps device-visible virtual addresses (also called device addresses or I/O addresses in this context) to physical addresses. Some units also provide memory protection from faulty or malicious devices.

An example IOMMU is the graphics address remapping table (GART) used by AGP and PCI Express graphics cards.

Prior to splitting the functionality of northbridge and southbridge between the CPU and Platform Controller Hub (PCH), I/O virtualization was not performed by the CPU but instead by the chipset.[1][2]

Advantages[edit]

The advantages of having an IOMMU, compared to direct physical addressing of the memory, include:

For system architectures in which port I/O is a distinct address space from the memory address space, an IOMMU is not used when the CPU communicates with devices via I/O ports. In system architectures in which port I/O and memory are mapped into a suitable address space, an IOMMU can translate port I/O accesses.

Disadvantages[edit]

The disadvantages of having an IOMMU, compared to direct physical addressing of the memory, include:[4]

Virtualization[edit]

When an operating system is running inside a virtual machine, including systems that use paravirtualization, such as Xen, it does not usually know the host-physical addresses of memory that it accesses. This makes providing direct access to the computer hardware difficult, because if the guest OS tried to instruct the hardware to perform a direct memory access (DMA) using guest-physical addresses, it would likely corrupt the memory, as the hardware does not know about the mapping between the guest-physical and host-physical addresses for the given virtual machine. The corruption is avoided because the hypervisor or host OS intervenes in the I/O operation to apply the translations, causing a delay in the I/O operation.

An IOMMU can solve this problem by re-mapping the addresses accessed by the hardware according to the same (or a compatible) translation table that is used to map guest-physical address to host-physical addresses.[5]

Published specifications[edit]

See also[edit]

References[edit]

  1. ^ "Intel platform hardware support for I/O virtualization". intel.com. 2006-08-10. Archived from the original on 2007-01-20. Retrieved 2014-06-07. 
  2. ^ "Desktop Boards: Compatibility with Intel Virtualization Technology (Intel VT)". intel.com. 2014-02-14. Retrieved 2014-06-07. 
  3. ^ "Physical Address Extension — PAE Memory and Windows". Microsoft Windows Hardware Development Central. 2005. Retrieved 2008-04-07. 
  4. ^ Muli Ben-Yehuda, Jimi Xenidis, Michal Ostrowski (2007-06-27). "Price of Safety: Evaluating IOMMU Performance" (PDF). Proceedings of the Linux Symposium 2007. Ottawa, Ontario, Canada: IBM Research. Retrieved 2013-02-28. 
  5. ^ "Xen FAQ: In DomU, how can I use 3D graphics". Retrieved 2006-12-12. 
  6. ^ "AMD I/O Virtualization Technology (IOMMU) Specification Revision 2.0" (PDF). amd.com. 2011-03-24. Retrieved 2014-01-11. 
  7. ^ "Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification" (PDF). Retrieved 2012-02-04. 
  8. ^ "DVMA Resources and IOMMU Translations". Retrieved 2007-04-30. 
  9. ^ "Logical Partition Security in the IBM eServer pSeries 690". Retrieved 2007-04-30. 
  10. ^ "I/O Virtualization specifications". Retrieved 2007-05-01. 
  11. ^ "ARM SMMU". Retrieved 2013-05-13. 
  12. ^ "ARM Virtualization Extensions". Retrieved 2013-05-13. 

External links[edit]