Don't-care term

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Don't⋅care terms chosen to get minimal circuit
Karnaugh map for lower left segment
Digits in 7-segment display
00Dígito c0.svgDígito c1.svgDígito c3.svgDígito c2.svg
01Dígito c4.svgDígito c5.svgDígito c7.svgDígito c6.svg
10Dígito c8.svgDígito c9.svg

In digital logic, a don't-care term for a function is an input-sequence (a series of bits) that is known never to occur. The designer of a logic circuit to implement the function need not care about such inputs, but can choose the circuit's output arbitrarily, usually such that the easiest circuit results (minimization). Examples of don't-care terms are the binary values 1010 through 1111 (10 through 15 in decimal) for a function that takes a binary-coded decimal (BCD) value, because a BCD value never takes on such values; in the pictures, the circuit computing the lower left bar of a 7-segment display can be minimized to a b + a c + a d by an appropriate choice of circuit outputs for dcba=1010...1111.

Don't-care terms are important to consider in minimizing logic circuit design, using Karnaugh maps and the Quine–McCluskey algorithm. Don't care optimization can also be used in the development of highly size-optimized assembly or machine code taking advantage of side effects.[citation needed]

X value[edit]

"Don't care" may also refer to an unknown value in a multi-valued logic system, in which case it may also be called an X value. In the Verilog hardware description language such values are denoted by the letter "X". In the VHDL hardware description language such values are denoted (in the standard logic package) by the letter "X" (forced unknown) or the letter "W" (weak unknown).[1]

An X value does not exist in hardware. In simulation, an X value can result from two or more sources driving a signal simultaneously, or the stable output of a flip-flop (electronics) not having been reached. In synthesized hardware, however, the actual value of such a signal will be either 0 or 1, but will not be determinable from the circuit's inputs.[1]

See also[edit]


  1. ^ a b David Naylor and Simon Jones (1997). Vhdl: A Logic Synthesis Approach. Springer. pp. 14–15,219,221. ISBN 0-412-61650-5. 

External sources[edit]